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The TPU is a coprocessor available on many Freescale microcontrollers. Depending on the
microcontroller, 1, 2 or 3 TPUs are present.
Each TPU provides 16 I/O pins which can be independently managed by microcoded TPU functions.
The TPU processor is a 16 bit RISC engine. It executes one instruction
every 2 CPU clocks and each instruction can cause multiple actions so it's a powerful addition to any CPU.
Associated with each I/O channel is a set of comparators and capture registers which can be configured by the microcode. TPU functions run as a cooperative multitasking code set. A variety of conditions including time and pin transitions are examined to select a specific function entry point. Microcode functions are associated with a given channel but they can read or drive any other channel pin. A small dual port RAM provides a data interchange between the TPU and CPU and variable storage for TPU functions. Each channel has a fully vectored CPU interrupt which can be asserted under microcode control. The TPU was designed with the auto industry in mind. It can handle sparks and injectors for a 12 cylinder engine doing 8000 RPM with ease. Faster devices can support systems with multiple signals in the 100 KHz range quite well. TPU functions don't have to do anything with I/O pins. A function can simply be a compute resource for the CPU. We have developed numerous CPU encode/decode and digital filter functions which offload the CPU. While the TPU's numerical instructions are limited, it is possible to implement complicated algorithms if processing time allows. Our most complicated math function to date contains a trapezoidal filter using 64 bit math. TPU functions do not necessarily require interaction with the CPU. Our automotive engine control system can maintain a running engine while the CPU reboots. |